Some memory systems include a multi-level cache system. Upon receipt from a processor core by a memory controller of a request for a particular memory address, the memory controller determines if data associated with the memory address is present in a first level cache (L1). If the data is present in the L1 cache, the data is returned from the L1 cache. If the data associated with the memory address is not present in the L1 cache, then the memory controller accesses a second level cache (L2) which may be larger and thus hold more data than the L1 cache. If the data is present in the L2 cache, the data is returned from the L2 cache to the processor core and a copy also is stored in the L1 cache in the event that the same data is again requested. Additional memory levels of the hierarchy are possible as well.